`timescale 1ns / 1ps

module display_half_driver_sim();
    reg clk_i = 'b0;
    reg [3:0] display_en = 'b1111;
    reg [11:0] display_num = 'o1234;
    reg [3:0] display_extra = 'b0000;
    wire [7:0] decoded_num;
    wire [3:0] digit_en_o; 
    display_half_driver UUT(clk_i, display_en, display_num, display_extra, decoded_num, digit_en_o);
    
    always #1 begin clk_i = ~clk_i; end
    
    initial begin
        #40 display_extra[2] = 'b1;
        #40 $stop;
    end
endmodule
